This invention relates to phase locked loop (“PLL”) circuitry, and more particularly to digital phase locked loop (“DPLL”) circuitry.
PLL circuitry is a frequently needed type of circuitry. For example, in the reception of clock data recovery (“CDR”) signals, PLL circuitry may be used to help match the frequency and phase of a controllably variable clock signal to the clock information that is embedded in the received CDR signal. The frequency-and-phase-matched clock signal can be used as a “recovered” clock signal, which is useful, for example, in processing the data information that is also recovered from the CDR signal.
PLL circuitry may include a “digital” portion (“DPLL circuitry”). For example, after a frequency match has been achieved, several versions (“candidate clock signals”) of the frequency-matched clock signal may be produced. Each of these versions is shifted somewhat in phase relative to the other versions. The digital portion of the PLL circuitry may be used to make a final selection of the version that has the best phase match. Relative stability in such a final selection is important (e.g., to avoid final selections that change too soon (prematurely) or too often (“hunting”)). Also, it can be important to avoid “glitches” in the recovered clock signal. Glitches can be associated with certain types of changes in the final selection of the clock signal version to be output as the recovered clock signal. A glitch is typically one or more signal transitions that are fragmentary or too close to one another or to other transitions in the recovered clock signal (i.e., signal transition spacings that are too small a fraction of a proper recovered clock signal cycle).